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74AUP2G02GM,125

Nexperia USA Inc.
RoHS
RoHS RoHS compliant
Package 8-XFQFN Exposed Pad
Category Integrated Circuits (ICs) / Logic - Gates and Inverters
Description NOR 74AUP2G02 e4 74AUP logic gate circuit 6.4ns @ 3.3V 30pF 0.5mm 4mA 4mA 3.6V
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Inventory: 1052360
Minimum: 1
Total Price: USD $0.09
Unit Price: USD $0.0924
≥1 USD $0.0924

Technical Details

Supply Chain

Factory Lead Time 20 Weeks

Physical

Contact Plating Gold
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-XFQFN Exposed Pad
Number of Pins 8

Technical

Operating Temperature -40°C~125°C
Packaging Tape & Reel (TR)
Published 2010
Series 74AUP
JESD-609 Code e4
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position QUAD
Peak Reflow Temperature (Cel) 260
Number of Functions 1
Supply Voltage 1.1V
Terminal Pitch 0.5mm
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number 74AUP2G02
Pin Count 8
Number of Outputs 1
Supply Voltage-Max (Vsup) 3.6V
Propagation Delay 6.4 ns
Quiescent Current 500nA
Turn On Delay Time 19.9 ns
Family AUP/ULP/V
Logic Function NOR
Current - Output High, Low 4mA 4mA
Logic Type NOR Gate
Number of Gates 2
Max Propagation Delay @ V, Max CL 6.4ns @ 3.3V, 30pF
Logic Level - Low 0.7V ~ 0.9V
Logic Level - High 1.6V ~ 2V

Dimensions

Height Seated (Max) 0.5mm

Compliance

Radiation Hardening No
RoHS Status ROHS3 Compliant
Lead Free Lead Free

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