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74AUP1G04FS3-7

Diodes Incorporated
RoHS
RoHS RoHS compliant
Package 4-XFDFN Exposed Pad
Category Integrated Circuits (ICs) / Logic - Gates and Inverters
Description S-PDSO-N4 74AUP Tape & Reel (TR) AUP/ULP/V logic gate circuit 5.4ns @ 3.3V 30pF 0.35mm 4mA 4mA 3.6V
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Inventory: 455
Minimum: 1
Total Price: USD $0.34
Unit Price: USD $0.34188
≥1 USD $0.34188
≥10 USD $0.276276
≥100 USD $0.252806
≥500 USD $0.188126
≥1000 USD $0.170497
≥3000 USD $0.141114

Technical Details

Supply Chain

Factory Lead Time 18 Weeks

Physical

Mount Surface Mount
Mounting Type Surface Mount
Package / Case 4-XFDFN Exposed Pad

Technical

Operating Temperature -40°C~125°C
Packaging Tape & Reel (TR)
Published 2015
Series 74AUP
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 4
Capacitance 6.1pF
Subcategory Gates
Packing Method TAPE AND REEL
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Terminal Form NO LEAD
Number of Functions 1
Supply Voltage 3V
Terminal Pitch 0.48mm
Pin Count 4
JESD-30 Code S-PDSO-N4
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.6V
Supply Voltage-Min (Vsup) 0.8V
Number of Circuits 1
Propagation Delay 5.4 ns
Quiescent Current 500nA
Turn On Delay Time 33.6 ns
Family AUP/ULP/V
Number of Inputs 1
Current - Output High, Low 4mA 4mA
Logic Type Inverter
Max Propagation Delay @ V, Max CL 5.4ns @ 3.3V, 30pF
Prop. Delay@Nom-Sup 27 ns
Schmitt Trigger NO
Logic Level - Low 0.7V ~ 0.9V
Logic Level - High 1.6V ~ 2V

Dimensions

Height Seated (Max) 0.35mm
Length 0.8mm
Width 0.8mm

Compliance

RoHS Status ROHS3 Compliant
Lead Free Lead Free

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