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74AUP2G04FW3-7

Diodes Incorporated
RoHS
RoHS RoHS compliant
Package 6-XFDFN
Category Integrated Circuits (ICs) / Logic - Gates and Inverters
Description e3 74AUP Cut Tape (CT) AUP/ULP/V logic gate circuit 5.4ns @ 3.3V 30pF 280mum 4mA 4mA 1.6V-2V
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Inventory: 1292
Minimum: 1
Total Price: USD $1.35
Unit Price: USD $1.34862
≥1 USD $1.34862
≥10 USD $1.107225
≥100 USD $1.072313
≥500 USD $1.0374
≥1000 USD $1.003485

Technical Details

Physical

Contact Plating Tin
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 6-XFDFN
Number of Pins 6

Technical

Operating Temperature -40°C~125°C TA
Packaging Cut Tape (CT)
Published 2014
Series 74AUP
JESD-609 Code e3
Part Status Discontinued
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 6
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Peak Reflow Temperature (Cel) 260
Number of Functions 2
Supply Voltage 3V
Terminal Pitch 0.3mm
Time@Peak Reflow Temperature-Max (s) 30
Supply Voltage-Min (Vsup) 0.8V
Number of Circuits 2
Propagation Delay 5.4 ns
Quiescent Current 500nA
Turn On Delay Time 6.9 ns
Family AUP/ULP/V
Current - Output High, Low 4mA 4mA
Logic Type Inverter
Max Propagation Delay @ V, Max CL 5.4ns @ 3.3V, 30pF
Logic Level - Low 0.7V ~ 0.9V
Logic Level - High 1.6V ~ 2V
Schmitt Trigger Input No

Dimensions

Height 280μm
Length 900μm
Width 1mm

Compliance

RoHS Status ROHS3 Compliant

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