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74AUP1G132GX,125

Nexperia USA Inc.
RoHS
RoHS RoHS compliant
Package 4-XFDFN Exposed Pad
Category Integrated Circuits (ICs) / Logic - Gates and Inverters
Description NAND 74AUP1G132 S-PDSO-N5 74AUP logic gate circuit 7.8ns @ 3.3V 30pF 0.35mm 4mA 4mA 3.6V
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Inventory: 125733
Minimum: 1
Total Price: USD $0.11
Unit Price: USD $0.11088
≥1 USD $0.11088

Technical Details

Supply Chain

Factory Lead Time 13 Weeks

Physical

Mount Surface Mount
Mounting Type Surface Mount
Package / Case 4-XFDFN Exposed Pad

Technical

Operating Temperature -40°C~125°C
Packaging Tape & Reel (TR)
Series 74AUP
JESD-609 Code e3
Feature Schmitt Trigger
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 5
Terminal Finish Tin (Sn)
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Terminal Form NO LEAD
Number of Functions 1
Supply Voltage 1.1V
Terminal Pitch 0.48mm
Base Part Number 74AUP1G132
Pin Count 5
JESD-30 Code S-PDSO-N5
Supply Voltage-Max (Vsup) 3.6V
Supply Voltage-Min (Vsup) 0.8V
Number of Circuits 1
Propagation Delay 7.8 ns
Quiescent Current 500nA
Family AUP/ULP/V
Logic Function NAND
Number of Inputs 2
Current - Output High, Low 4mA 4mA
Logic Type NAND Gate
Max Propagation Delay @ V, Max CL 7.8ns @ 3.3V, 30pF
Logic Level - Low 0.1V ~ 0.88V
Logic Level - High 0.6V ~ 2.29V

Dimensions

Height Seated (Max) 0.35mm
Length 0.8mm
Width 0.8mm

Compliance

RoHS Status ROHS3 Compliant

Alternative Model

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