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ISPPAC-CLK5620AV-01T100C
Lattice Semiconductor CorporationRoHS
/
Package 100-LQFP
Category Integrated Circuits (ICs) / Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Description
HSTL LVCMOS LVDS LVPECL LVTTL SSTL 100-LQFP ISPPAC-CLK5620A PLL BASED CLOCK DRIVER clock generator circuit 3.6V 400MHz 0.5mm 8.8ns
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Technical Details
Physical
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 100-LQFP
Number of Pins 100
Compliance
RoHS Status Non-RoHS Compliant
Lead Free Lead Free
Technical
Operating Temperature 0°C~70°C
Packaging Tray
Published 2000
Series ispClock?
JESD-609 Code e0
Pbfree Code no
Part Status Obsolete
Moisture Sensitivity Level (MSL) 3 (168 Hours)
Number of Terminations 100
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
Subcategory Clock Drivers
Voltage - Supply 3V~3.6V
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 240
Number of Functions 1
Supply Voltage 3.3V
Terminal Pitch 0.5mm
Reach Compliance Code not_compliant
Time@Peak Reflow Temperature-Max (s) 30
Base Part Number ISPPAC-CLK5620A
Output EHSTL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
Pin Count 100
Qualification Status Not Qualified
Supply Voltage-Max (Vsup) 3.6V
Power Supplies 3.3V
Supply Voltage-Min (Vsup) 3V
Number of Circuits 1
Frequency (Max) 400MHz
Family 5600
Input HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL
Ratio - Input:Output 2:20
Logic IC Type PLL BASED CLOCK DRIVER
PLL Yes with Bypass
Differential - Input:Output Yes/Yes
Propagation Delay (tpd) 8.8 ns
Divider/Multiplier Yes/No
fmax-Min 400 MHz
Same Edge Skew-Max (tskwd) 0.05 ns
Alternative Model
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