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PSD913F2-90J

STMicroelectronics
RoHS
/
Package PLCC
Category Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array)
Description CMOS COMMERCIAL Non-RoHS Compliant J BEND field programmable gate array 70C 0.0002A 1310720Bits 9e-8ns
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Technical Details

Physical

Package / Case PLCC
Surface Mount YES

Technical

JESD-609 Code e0
Number of Terminations 52
ECCN Code EAR99
Terminal Finish Tin/Lead (Sn/Pb)
HTS Code 8542.39.00.01
Subcategory Other Microprocessor ICs
Technology CMOS
Terminal Position QUAD
Terminal Form J BEND
Peak Reflow Temperature (Cel) NOT SPECIFIED
Supply Voltage 5V
Terminal Pitch 1.27mm
Reach Compliance Code not_compliant
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Pin Count 52
JESD-30 Code S-PQCC-J52
Qualification Status Not Qualified
Operating Temperature (Max) 70°C
Supply Voltage-Max (Vsup) 5.5V
Power Supplies 5V
Temperature Grade COMMERCIAL
Supply Voltage-Min (Vsup) 4.5V
Number of I/O 27
Number of Ports 4
uPs/uCs/Peripheral ICs Type PARALLEL IO PORT, GENERAL PURPOSE
Standby Current-Max 0.0002A
Access Time (Max) 9e-8 ns
UV Erasable N
ROM Size (bits) 1310720Bits

Dimensions

Height Seated (Max) 4.57mm
Length 19.1262mm
Width 19.1262mm

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