XQ2VP70-6EF1704I

Xilinx

RoHS

Package /

Category Integrated Circuits (ICs) / Embedded - FPGAs (Field Programmable Gate Array)

Description CMOS Non-RoHS Compliant BALL BOTTOM field programmable gate array 0.32ns 1.425V 3.45mm

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Technical Details

Physical

Surface Mount YES

Technical

JESD-609 Code e0

Number of Terminations 1704

ECCN Code 3A001.A.7.A

Terminal Finish Tin/Lead (Sn/Pb)

HTS Code 8542.39.00.01

Technology CMOS

Terminal Position BOTTOM

Terminal Form BALL

Peak Reflow Temperature (Cel) NOT SPECIFIED

Supply Voltage 1.5V

Terminal Pitch 1mm

Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED

Pin Count 1704

JESD-30 Code S-PBGA-B1704

Supply Voltage-Max (Vsup) 1.575V

Supply Voltage-Min (Vsup) 1.425V

Organization 8272 CLBS

Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY

Combinatorial Delay of a CLB-Max 0.32 ns

Number of CLBs 8272

Dimensions

Height Seated (Max) 3.45mm

Length 42.5mm

Width 42.5mm

Compliance

RoHS Status Non-RoHS Compliant

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